Semiconductor memory device and method of reading a data therefr

Details Semiconductor memory device and method of reading a data therefr Semiconductor memory device and method of reading a data therefr

1996-11-25

1998-12-15

Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257317, 257319, H01L 2900

Patent

active

058500910

ABSTRACT:
A semiconductor memory device wherein source lines of a memory cell array constituted by a plurality of memory cells arranged in the form of a matrix at intersecting points of word lines and bit lines are arranged in a row direction or a column direction and the source lines of the nonselected rows or the nonselected columns are inversely biased with respect to the semiconductor substrate, thereby to prevent erroneous reading by the leakage current at the time of reading data and further reduce the write current at the time of writing. Further, the read operation is kept from deteriorating by reducing the amplitude of the source line at the time of reading by setting the inverse bias voltage at a minimum constant voltage smaller than the power source voltage.

REFERENCES:
patent: 5388065 (1995-02-01), Yoneda
patent: 5397725 (1995-03-01), Wolstenholme et al.
patent: 5409854 (1995-04-01), Bergemont
patent: 5548146 (1996-08-01), Kuroda et al.
patent: 5587948 (1996-12-01), Nakai
patent: 5589699 (1996-12-01), Araki
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5627779 (1997-05-01), Odake et al.
patent: 5637895 (1997-06-01), Iwata et al.

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