Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-04-11
1998-06-02
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438624, 438626, 438627, 438633, 438639, H01L 2128
Patent
active
057599068
ABSTRACT:
An improved method for making a planar intermetal dielectric layer (IMD) for multilevel electrical interconnections on ULSI circuits is achieved. The method involves forming metal lines on which is deposited a conformal PECVD oxide. A multilayer of spin-on glass, composed of at least four layers, is deposited and baked at elevated temperatures and long times after each layer to minimize the poisoned via problem on product with minimum feature sizes greater than 0.35 um. A multilayer of a low dielectric constant polymer can also be used to reduce the RC time delay on product having minimum feature sizes less than 0.35 um. After depositing a SiO.sub.2 on the SOG, or depositing a Fluorine-doped Silicon Glass (FSG) on the low k polymer, the layer is partially chemical/mechanically polished to provide the desired more global planar IMD. This eliminates the necessity of polishing back the SOG or polymer, which is difficult to achieve with the current technologies. Via holes are then etched in the IMD, and a FSG insulating layer is deposited and etched back to form sidewall spacers in the via holes to prevent outgassing from the SOG or low k polymer, and the next level of metal interconnections are formed. The method can be repeated to achieve a multilevel of planar metal interconnections for ULSI circuits.
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Ackerman Stephen B.
Bilodeau Thomas G.
Industrial Technology Research Institute
Niebling John
Saile George O.
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