Patent
1997-06-30
1999-01-26
Hua, Ly
39518221, G06F 1128, G06F 1130
Patent
active
058646566
ABSTRACT:
A system for automatic fault detection and recovery in a computer system includes: a system fault detector, a halt time duration counter, and program and hardware recovery signal generators. The system fault detector is connected to a plurality of bus signal lines of a computer system to produce an output signal in response to an existence of an operating signal in the system bus. The halt time counter is operated in response to the output signal of the fault detector and clock signals to produce a set of count values each representing the passage of a predetermined time duration after a vanishing of the output signal of the fault detector. The program recovery signal generator produces a system management interrupt (SMI) signal when seven minutes have elapsed from the detection of the system halt. Also, the hardware recovery signal generator produces a reset signal when eight minutes have elapsed from the detection of the system halt. Further, the recovery system includes a selector consisting of a one-bit register for storing an initial value for enabling operation of the fault detector at the start of the computer system, the selector being connected to the system bus and changing its initial value in response to a BIOS program from the system bus to disable the operation of the fault detector. The computer system is set to save the data processed in an application program in response to the SMI signal.
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Bushnell Esq. Robert E.
Hua Ly
Samsung Electronics Co,. Ltd.
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