Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-08-14
1999-11-09
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438668, 438669, 438673, 438637, 438926, H01L 2144
Patent
active
059813849
ABSTRACT:
A technique is disclosed for general IC structures to modify the layout of electrically unisolated metal lines before patterning same so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer. Upon such standardization of metal line spacing, the intermetal dielectric will be planarized in a single process step of deposition. Circuit layout design modifications can be made by adding electrically isolated dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing between the metal lines and dummy metal features. As the nonstandard spacing between metal lines becomes standardized, an internetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.
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Gurley Lynne A.
Micro)n Technology, Inc.
Niebling John F.
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