Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1996-10-17
1999-11-09
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438587, 438592, 438596, 438655, 438657, 438666, H01L 213205, H01L 21324
Patent
active
059813679
ABSTRACT:
Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.
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patent: 5576228 (1996-11-01), Chen et al.
patent: 5616948 (1997-04-01), Pfiester
patent: 5698072 (1997-12-01), Fukuda
W.R. Hunter, et al., New Edge-Defined Vertical-Etch Approaches for Submircometer Mosfet Fabrication, IEEE, 1980, pp. 764-767.
Micro)n Technology, Inc.
Nguyen Ha Tran
Niebling John F.
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