Method for reducing capacitive coupling between conductive lines

Details Method for reducing capacitive coupling between conductive lines Method for reducing capacitive coupling between conductive lines

1996-04-29

1998-12-29

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438620, 438598, 438637, 438666, 438669, H01L 214763

Patent

active

058541284

ABSTRACT:
An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

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