Interconnect and resistor for integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor...

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Details

257538, 257755, H01L 2904, H01L 2702, H01L 2934, H01L 2348

Patent

active

051826275

ABSTRACT:
A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.

REFERENCES:
patent: 4948747 (1990-08-01), Pfiester
patent: 4961103 (1990-10-01), Saitoh et al.
patent: 4968645 (1990-11-01), Baldi et al.
patent: 5068201 (1991-11-01), Spinner, III et al.

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