Low power ECL/MOS level converting circuit and memory device and

Details Low power ECL/MOS level converting circuit and memory device and Low power ECL/MOS level converting circuit and memory device and

1990-04-27

1994-10-25

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518905, 365177, 307475, 307446, G11C 11409, G11C 11419, H03K 190175, H03K 1908

Patent

active

053595530

ABSTRACT:
A level converting circuit comprises first and second complementary metal oxide semiconductor (CMOS) inverter circuits, and first and second N-Channel metal oxide semiconductor (NMOS) transistors. The first CMOS inverter circuit and the first transistor are connected in series between a relatively high power supply voltage and a relatively low power supply voltage. The second CMOS inverter circuit and the second NMOS transistor are connected in series between the relatively high power supply voltage and the relatively low power supply voltage. Complementary emitter coupled logic (ECL) level signals are converted into MOS level signals by the first and second CMOS inverter circuits. Current flow from the relatively high power supply voltage to the relatively low power supply voltage is inhibited by the first and second NMOS transistors. The level converting circuit can be used to interface a metal oxide semiconductor (MOS) memory cell array to a bipolar peripheral circuit.

REFERENCES:
patent: 4039862 (1977-08-01), Dingwall et al.
patent: 4697109 (1987-09-01), Honme et al.
patent: 4710647 (1987-12-01), Young
patent: 4797583 (1989-01-01), Ueno et al.

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