Integrated chip package with reduced dimensions and leads expose

Details Integrated chip package with reduced dimensions and leads expose Integrated chip package with reduced dimensions and leads expose

1996-08-23

1998-06-23

Arroyo, Teresa M.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257676, 257692, 257686, H01L 2348, H01L 23495, H01L 2352, H01L 2302

Patent

active

057708886

ABSTRACT:
An improved package is thinner with increased memory capacity and improved heat emission effect. The package includes a plurality of leads, where each lead comprises a first connection lead and a second connection lead with upper and lower surfaces. An integrated chip, such as a semiconductor chip, is attached to a portion of the upper surface of the first connection lead. The chip and leads are molded such that the lower surface of the first connection leads and upper surface of the second connection leads are exposed.

REFERENCES:
patent: 4857989 (1989-08-01), Mori et al.
patent: 5157480 (1992-10-01), McShane et al.
patent: 5214307 (1993-05-01), Davis
patent: 5223739 (1993-06-01), Katsumata et al.
patent: 5394010 (1995-02-01), Tazawa et al.
patent: 5406124 (1995-04-01), Morita et al.
patent: 5428248 (1995-06-01), Cha
patent: 5436500 (1995-07-01), Park et al.
patent: 5444301 (1995-08-01), Song et al.

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