Multi-level transistor fabrication method with a patterned upper

Details Multi-level transistor fabrication method with a patterned upper Multi-level transistor fabrication method with a patterned upper

1996-10-08

1998-06-23

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438303, 438618, H01L 2100, H01L 2184

Patent

active

057704821

ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.

REFERENCES:
patent: 5470776 (1995-11-01), Ryou
patent: 5492851 (1996-02-01), Ryou
patent: 5610094 (1997-03-01), Ozaki et al.

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