Multi write port register

Details Multi write port register Multi write port register

1995-12-05

1997-05-13

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

36523008, 36518905, 36518908, 365194, G11C 700, G11C 800

Patent

active

056299010

ABSTRACT:
A multi-write port register is provided with a local clock buffer (LCB) to control a gate on the input port to reduce potential timing hazards. The LCB provides flexible logic function and is controlled by a clock and word-line inputs. In addition, the LCB may also have bit-line and/or field mask inputs. The LCB handles all the timing critical functions that all the Word Lines (WLs) previously performed in conventional multi-write port registers, thus providing a substantial performance increase.

REFERENCES:
patent: 5212665 (1993-05-01), Ihara
patent: 5247484 (1993-09-01), Watanabe
patent: 5260908 (1993-11-01), Ueno
patent: 5285413 (1994-02-01), Miyauchi et al.
patent: 5287323 (1994-02-01), Takahashi et al.
patent: 5289427 (1994-02-01), Nicholes et al.
patent: 5355335 (1994-10-01), Katsuno
patent: 5377157 (1994-12-01), Matsumoto et al.
patent: 5384734 (1995-01-01), Tsujihashi et al.
patent: 5481495 (1996-01-01), Henkel et al.

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