Method of fabricating metal contact of ultra-large-scale integra

Details Method of fabricating metal contact of ultra-large-scale integra Method of fabricating metal contact of ultra-large-scale integra

1995-10-18

1998-03-10

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438164, 438300, 438657, H01L 2184

Patent

active

057260818

ABSTRACT:
In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

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patent: 5567966 (1996-10-01), Hwang
Y. yamaguchi et al., IEEE Trans. Electron Dev., 39(5)(1992)1179 "Self-Aligned Silicide . . . Untra-Thin SIMOX MOSFET's".
D. Hisamoto et al., IEDM '92 Proc., p. 829, "Ultra-Thin SOI CMOS with Selective CVD W . . . ".
S. Wolf, "Silicon Processing for the VLSI Era" vol. II, pp. 144-149 Jun. 1990.

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