Microprocessor having a cache memory system using multi-level ca

Details Microprocessor having a cache memory system using multi-level ca Microprocessor having a cache memory system using multi-level ca

1996-03-13

1999-06-29

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711128, 711137, G06F 1208, G06F 1300

Patent

active

059182458

ABSTRACT:
A cache structure for a microprocessor which provides set-prediction information for a separate, second-level cache, and a method for improving cache accessing, are provided. In the event of a first-level cache miss, the second-level set-prediction information is used to select the set in an N-way off-chip set-associative cache. This allows a set-associative structure to be used in a second-level cache (on or off chip) without requiring a large number of traces and/or pins. Since set-prediction is used, the subsequent access time for a comparison to determine that the correct set was predicted is not in the critical timing path unless there is a mis-prediction or a miss in the second-level cache. Also, a cache memory can be partitioned into M sets, with M being chosen so that the set size is less than or equal to the page size, allowing a cache access before a TLB translation is done, further speeding the access.

REFERENCES:
patent: 5235697 (1993-08-01), Steely, Jr. et al.
patent: 5392414 (1995-02-01), Yung
patent: 5418922 (1995-05-01), Liu
patent: 5548739 (1996-08-01), Yung
Kessler R. E. et al., "Inexpensive Implementation of Set-Associativity," in Computer Architecture Conference Proceedings, Washington, US, vol. 17, No. 3, Jun. 17, 1989, pp. 131-139, XP000035297.

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