Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-03-08
1999-04-06
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39518203, G06F 1116
Patent
active
058931520
ABSTRACT:
Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart memory entry to trace inconsistencies between the cache entry and the memory entry and to correct the cache entry. A page table entry in memory with a zero mapping mark is checked against a counterpart page entry in a translation lookaside buffer. Inconsistencies between the page table entry with a zero mapping mark and the existence of a counterpart page entry in the translation lookaside buffer is traced. The inconsistency is corrected by deleting the counterpart page entry in the translation lookaside buffer. Address mapping is checked comparing a page entry in the translation lookaside buffer against a counterpart page table entry in the memory. Inconsistencies between the page entry and the page table entry are traced and corrected.
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Fuller Billy J.
Passmore Dale R.
Chan Eddie P.
Encarnacion Yamir
Kubida William J.
Pinto James A.
Sun Microsystems Inc.
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