Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-04
1999-04-06
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711146, 711163, 711169, 711158, 711145, G06F 1208, G06F 1318
Patent
active
058931511
ABSTRACT:
An apparatus for maintaining cache coherency for snoop operations includes a processor core for fetching, decoding, and executing instructions, a data cache coupled to the processor core for providing data to the processor core and for receiving data from the processor core, and a system bus coupling the processor core to the data cache. The apparatus further includes a snoop scheduler coupled to the processor core, the data cache, and the system bus, where the snoop scheduler is coupled to receive addresses from the system bus. The snoop scheduler also determines if snoop operations are orthogonal and schedules one or more out-of-order and at least partially overlapping snoop operations. Determining which snoop operations are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.
REFERENCES:
patent: 5168547 (1992-12-01), Miller et al.
patent: 5208914 (1993-05-01), Wilson et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5363498 (1994-11-01), Sakuraba et al.
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5566319 (1996-10-01), Lenz
patent: 5586331 (1996-12-01), Levenstein
patent: 5611058 (1997-03-01), Moore et al.
patent: 5611071 (1997-03-01), Martinez, Jr.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5623670 (1997-04-01), Bohannon et al.
patent: 5696910 (1997-12-01), Pawlowski
Gharachorloo, et al., "Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors", SIGARCH Computer Architecture News., Apr. 1991, vol. 19, No. 2, p. 246.
Bragdon Reginald G.
Intel Corporation
LandOfFree
Method and apparatus for maintaining cache coherency in a comput does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for maintaining cache coherency in a comput, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for maintaining cache coherency in a comput will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1381959