Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-11-10
1999-04-06
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711129, G06F 1208
Patent
active
058931481
ABSTRACT:
A stack cache memory mechanism and method for managing the mechanism are provided. The mechanism comprises a data array including a plurality of storage elements in which stack data may be stored, and a plurality of individual stack tag sets for identifying beginning and ending locations of a corresponding plurality of individual stacks contained within the data array. Each of the individual stack tag sets comprise (i) a first register for containing an address in the data array corresponding to the top of a stack associated with that individual stack tag set and (ii) a second register for containing an address in the data array corresponding to the bottom of a stack associated with that individual stack tag set. A backward pointer array comprises a plurality of backward pointers which map each of the plurality of stack tag sets to address locations in the data array. Allocation logic determines which of the data array storage elements are currently included within existing stacks, as defined by the plurality of backward pointers and the plurality of stack tag sets, and which of the data array storage elements are available to be allocated to a stack.
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Genduso Thomas B.
Leung Wan L.
Chan Eddie P.
Ellis Kevin L.
International Business Machines - Corporation
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