Multi-port static random access memory with fast write-thru sche

Details Multi-port static random access memory with fast write-thru sche Multi-port static random access memory with fast write-thru sche

1993-02-05

1995-12-05

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Multiple port access

36518404, 36523008, 365233, G11C 800

Patent

active

054735742

ABSTRACT:
A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder, an AND gate connected to a clock signal, the AND gate enabling a write port coupled to the latch of a memory cell. In the second stage, a read path is set up comprising a read address decoder selecting a read port, through which data is read from the cell latch to a data out buffer. To minimize the write-thru access time, the synchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses. Thus the write-thru access time becomes independent from the write time needed for overwriting the multi-port SRAM cell and equal to the read address access time achieved in a fully static or synchronous read operation.

REFERENCES:
patent: 4984204 (1991-01-01), Sato et al.
patent: 5001671 (1991-03-01), Koo et al.
patent: 5062081 (1991-10-01), Runaldue
patent: 5177706 (1993-01-01), Shinohara et al.

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