Semiconductor devices with pocket implant and counter doping

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257327, 257345, H01L 2701, H01L 2712, H01L 310397

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active

059172193

ABSTRACT:
A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').

REFERENCES:
patent: 4276095 (1981-06-01), Beilstein, Jr. et al.
patent: 4649629 (1987-03-01), Miller et al.
patent: 4869781 (1989-09-01), Euen et al.
patent: 5198687 (1993-03-01), Baliga
patent: 5362981 (1994-11-01), Sato et al.
patent: 5401994 (1995-03-01), Adan
patent: 5440160 (1995-08-01), Vinal
patent: 5463237 (1995-10-01), Funaki
patent: 5536957 (1996-07-01), Okumura
patent: 5548148 (1996-08-01), Bindal
patent: 5719430 (1998-02-01), Goto
M. Nandakumar, et al., "A Device Design Study of 0.25.mu.m Gate Length CMOS for 1V Low Power Applications", pp. 1-2.
Lisa T. Su, et al., "Tradeoffs of Current Drive vs. Short-Channel Effect in Deep-Submicrometer Bulk and SOI MOSFETs", 1994 IEEE, pp. 27.2.1-27.2.4.
M. Rodder, et al., "Design Process Dependence of 0.25.mu.m Gate Length CMOS for Imporved Performance and Reliability", 1994 IEEE, pp. 4.2.1-4.2.3.
Ghavam G. Shahidi, et al., "A Room Temperature 0.1 .mu.m CMOS on SOI", 1994 IEEE, pp. 2405-2411.
D. Hisamoto, et al., High-Performance Sub 0.1-.mu.m CMOS with Low-Resistance T-Shaped Gates Fabricated by Selective CVD-W, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 115-116.
G.G. Shahidi, et al. "Indium Channel Implant for Improved Short-Channel Behavior of Submicrometer NMOSFET's", 1993 IEEE, vol. 14, No. 8 Aug. pp. 409-411.
D.M. Boulin, et al. "A Symmetric 0.25.mu.m CMOS Technology for Low-Power, High-Performance ASCIC Applications Using 248nm DUV Lithography", 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 65-66.
Junji Koga, et al., "A Comprehensive Study of MOSFET Electron Mobility in Both Weak and Strong Inversion Regimes", IEDM94, pp. 18.6.1-18.6.4.
Y. Mii, et al., "An Ultra-Low Power 0.1 .mu.m CMOS", 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 9-10.
Takeski Andoh, et al., "Design Methodology for Low-Voltage MOSFETs", 1994 IEEE, pp. 4.4.1-4.4.4.
M. Rodder, et al., "Oxide Thickness Dependence of Inverter Delay and Device Reliability for 0.25 .mu.m CMOS Technology", IEEE, pp. 36.1.1-36.1.4.

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