Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-09-11
1999-06-29
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 54, G06F 1300
Patent
active
059163143
ABSTRACT:
In a digital computer with a cache comprised of N sets labeled 0 to N-1, cache tag memory for each set is divided into primary and mirror parts, each part with sufficient capacity to store a number of cache tags equal to the number of cache blocks storable in a cache memory associated with each set. Every modification or installation of cache tags in the primary part of a set x is accompanied or followed by identical modification or installation of cache tags in the mirror part of a set F(x), where F is a one-to-one function that maps the set of integers from 0 to N-1 onto itself. Cache tag lookup retrieves a first set of N cache tags from the primary part of each cache tag memory, and parity checking is performed on each tag. If a parity error is found, a set of cache tags is retrieved from the mirror part of the cache tag memories, and parity checking is again performed. If no error is found, cache processing proceeds normally. The cache tag memories are preferably SRAMs with a mirror enable bit driven by a cache controller such that tags are installed in or read from either a primary part or a mirror part of the SRAM depending on the value of the mirror enable bit.
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Berg Thomas B.
Datta Tapas
Beausoliel, Jr. Robert W.
Sequent Computer Systems, Inc.
Wright Norman Michael
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