Method of dry etching InAlAs and InGaAs lattice matched to InP

Details Method of dry etching InAlAs and InGaAs lattice matched to InP Method of dry etching InAlAs and InGaAs lattice matched to InP

1994-11-01

1995-12-12

Breneman, R. Bruce

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437126, 437133, H01L 2100

Patent

active

054746523

ABSTRACT:
A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM. By this procedure, functional InAlAs/InGaAs heterojunction bipolar transistors (HBTs) and HBT circuits can be fabricated using a dry etch. Also, self-aligned small geometry structures such as, for example, emitter HBTs and ring oscillator and comparator circuits composed of HBTs and both electronic and optical devices, such as lasers, can be fabricated using the above described procedures.

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