Semiconductor memory device having redundant memory cells

Details Semiconductor memory device having redundant memory cells Semiconductor memory device having redundant memory cells

1990-08-20

1993-03-23

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Bad bit

365203, 365233, 3652335, G11C 700

Patent

active

051970309

ABSTRACT:
A semiconductor memory device includes a memory cell array, a data readout circuit, a decoder circuit and an address transition detecting circuit which detects an address transition of an input address signal and which generates an address transition detection pulse. A redundancy circuit determines whether or not the input address signal indicates a defective memory cell and outputs a redundancy signal to the decoder so that the decoder selects one redundant memory cell in place of the specified defective memory cell. A pulse generator generates a pulse signal having a pulse duration time sufficient to reset the memory cell array and the data readout circuit before reading data from the memory cell array in a case where the redundancy circuit outputs the redundancy signal. The pulse duration time of the pulse signal starts from a time when the address transition detecting circuit generates the address transition signal.

REFERENCES:
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patent: 4849938 (1989-07-01), Furutani et al.
patent: 4905192 (1990-02-01), Nogami et al.
patent: 4953130 (1990-08-01), Houston
IEEE Journal of Solid State Circuits, vol. 20, No. 5, Oct. 1985, pp. 941-950, Sood et al., "A Fast 8K.times.8 CMOS SRAM With Internal Power Down Design Techniques".
IBM Technical Disclosure Bulletin, vol. 29, No. 4, Sep. 1986, pp. 1575-1578, "Method to Reconfigure Logic Signal Paths."

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