CMOS logic circuit and method of driving the same

Details CMOS logic circuit and method of driving the same CMOS logic circuit and method of driving the same

1998-06-18

2000-07-25

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326121, 326 15, 327534, H03K 190175, H03K 19094, H03K 19003, H03K 301

Patent

active

060940689

ABSTRACT:
A CMOS logic circuit including (a) a PMOS transistor, (b) an NMOS transistor, (c) a first coupling capacitor electrically connected only between a gate and a substrate of the PMOS transistor, and (d) a second coupling capacitor electrically connected between a gate and drain of the NMOS transistor, wherein the PMOS and NMOS transistors include substrate voltages which are made higher than associated reference voltages during rising edges of signals transmitted to the gates, and made lower than the associated reference voltages during falling edges of the signals. The gates of the PMOS and NMOS transistors are electrically connected to each other, drains of the PMOS and NMOS transistors are electrically connected to each other, and an input signal is introduced into the electrically connected gates, and an output signal is taken through the electrically connected drains.

REFERENCES:
patent: 3715603 (1973-02-01), Lerch
patent: 4571816 (1986-02-01), Dingwall
patent: 4810906 (1989-03-01), Shah et al.
patent: 5532620 (1996-07-01), Seo et al.
patent: 5644266 (1997-07-01), Chen et al.
patent: 5821783 (1998-10-01), Torimaru et al.
patent: 5970339 (1999-10-01), Choi

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