Cache coherency control method and multi-processor system using

Details Cache coherency control method and multi-processor system using Cache coherency control method and multi-processor system using

1997-04-23

1999-11-16

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711137, 711150, 711152, G06F 1200

Patent

active

059875712

ABSTRACT:
In a cache coherency control method of a multi-processor system comprising a plurality of cache systems of identical configuration-after "method", for quickly determining consistency of a data block designated by a cache coherency request issued by other cache system a multi-processor system using the same, systems have identical configuration and each of the cache systems includes a history table for storing an address included in an access request flowing over a shared bus and a history table control circuit. The history table control circuit determines whether an address of a received access request is stored in the history table, and when the address is stored in the history table, suppresses the operation of a cache control circuit for the access request, and alternatively when the address is not stored in the address table, conducts the operation of the cache control circuit for the access request.

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"Pentium Process or Architecture and Programming", Chapter 18, Intel Japan Company, Ltd.

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