Method of making a multi-layer interconnection structure

Details Method of making a multi-layer interconnection structure Method of making a multi-layer interconnection structure

1997-10-08

2000-07-25

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438631, 438669, 438763, 438778, 438787, H01L 214763

Patent

active

060936371

ABSTRACT:
A multi-layer interconnection structure in a semiconductor device has a interlevel dielectric layer of three SiO.sub.2 films. The first SiO.sub.2 film has a small thickness not lower than 25 nm and is formed by a dual-frequency plasma enhanced CVD process using alkoxysilane as a reactive gas. The second SiO.sub.2 film has a large thickness ranging between 300 and 800 nm and is formed on the first SiO.sub.2 film by an atmospheric pressure CVD process using a mixture of alkoxysilane and ozone as a reactive gas. The third SiO.sub.2 film has a thickness of 50 nm and is flattened by an etch-back process of the same together with an overlying sacrificial spin-on glass film. A second layer interconnect pattern is formed on or above the flattened third SiO.sub.2 film with an excellent reliability.

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patent: 5883001 (1999-03-01), Jin et al.
patent: 5953635 (1999-09-01), Andidoh

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