Method and apparatus for reducing skew between input signals and

Details Method and apparatus for reducing skew between input signals and Method and apparatus for reducing skew between input signals and

1997-10-29

2000-03-28

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 83, 326 93, 326108, 327162, 327263, H03K 19096

Patent

active

060436840

ABSTRACT:
The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input buffers of both the address path and the clock path include input buffer cells configured to reduce timing delay differences caused by process variations while minimizing current leakage. An exemplary input buffer cell described herein includes a first inverter stage with a pair of NMOS devices connected in series with a PMOS device and a second inverter stage having an additional PMOS device connected along a feedback path around an inverter. The PMOS device along the feedback path operates to assist the pair of NMOS devices to pull a voltage input to the inverter to a high logic state, when an input to the cell is held low, to prevent leakage current through the inverter. The pair of NMOS devices provide a first stage inverter substantially free of process variations. The PMOS device connected in series with the NMOS devices prevents current leakage through the NMOS devices when the input signal is held high.

REFERENCES:
patent: 4429375 (1984-01-01), Kobayashi et al.
patent: 4736123 (1988-04-01), Miyazawa et al.
patent: 4791323 (1988-12-01), Austin
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 4877978 (1989-10-01), Platt
patent: 4893281 (1990-01-01), Hashimoto
patent: 4978905 (1990-12-01), Hoff et al.
patent: 4979166 (1990-12-01), Yamada
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5136182 (1992-08-01), Fawal
patent: 5157284 (1992-10-01), O'Connell et al.
patent: 5305282 (1994-04-01), Choi
patent: 5386153 (1995-01-01), Voss et al.
patent: 5481581 (1996-01-01), Jonas, Jr. et al.
patent: 5493530 (1996-02-01), Lee et al.
patent: 5517138 (1996-05-01), Baltar et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5552723 (1996-09-01), Shigehara et al.
patent: 5587964 (1996-12-01), Rosich et al.
patent: 5625302 (1997-04-01), Covino et al.
patent: 5903174 (1999-05-01), Landry et al.
patent: B14638187 (1993-03-01), Boler et al.
Micron Semiconductor, Inc., MT58LC64K18B2 64K x 18 Synchronous SRAM, Revised Apr. 9, 1993, pp. 1-12.
Paradigm, PDM44018, 64K x 18 Fast CMOS Synchronous Static SRAM with Burst Counter, pp. 6-21 -6-29.
Hitachi Semiconductor, HM67B1864 Series (Target Spec.) 64K x 18 Bits Synchronous Fast Static RAM with Burst Counter and Self-Timed Write, Mar. 31, 1994, Prod. Preview, 10 pgs. total.
Motorola Semiconductor Technical Data, Product Review MCM67B618 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst counter and Self-Timed Write, Rev. 3 Jan. 1993, pp. 1-9.
Cypress Semiconductor, Preliminary CY7C1031 CY7C1032 64K x 18 Synchronous Cache RAM, Jan. 1993--Revised May 1993, pp. 1-13.

Affiliated with

Also associated with

Rating

Method and apparatus for reducing skew between input signals and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing skew between input signals and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing skew between input signals and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1329153