Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1998-01-08
2000-03-28
Tokar, Michael
Electronic digital logic circuitry
Interface
Logic level shifting
326 81, H03K 190175, H03K 19094
Patent
active
060436794
ABSTRACT:
A level shifter, irrespective of a variation of a threshold voltage, is capable of changing input signals of 0 volt and 5 volts to the signals of -10 volts and 10 volts, respectively, without using an additional voltage and an inverted signal even when a threshold voltage of an NMOS transistor is 4 volts. The level shifter includes a voltage distributor, e.g., two level output inverter generates a driving signal for an NMOS transistor and a PMOS transistor irrespective of a threshold voltage variation with respect to input voltages of 0 volts and 5 volts. A two level input inverter drives the PMOS transistor and NMOS transistor in response to a driving signal from the two level output inverter and outputs a signal, the level of which is reduced as much as a threshold voltage at voltages of -10 volts and 10 volts. An inverter outputs the output signals from the two level input inverter as voltage signals of -10 volts and 10 volts.
REFERENCES:
patent: 4578601 (1986-03-01), McAlister et al.
patent: 5034629 (1991-07-01), Kinugasa et al.
patent: 5266848 (1993-11-01), Nakagome et al.
patent: 5361006 (1994-11-01), Cooperman et al.
patent: 5378943 (1995-01-01), Dennard
LG Semicon Co. Ltd.
Tokar Michael
Tran A.
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