Processing methods of forming contact openings and integrated ci

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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Details

257758, 257760, 257308, H01L 2348, H01L 2946

Patent

active

059863471

ABSTRACT:
Methods of forming contact openings over a node location and related integrated circuitry are described. In one aspect of the invention, a node location is formed within a semiconductive substrate adjacent an isolation oxide region. A layer of material is formed over the node location and a contact opening is etched through the layer of material to outwardly expose a node location planar upper surface. In one preferred implementation, the contact opening includes an inner surface portion which faces generally transversely away from the isolation oxide region and which defines an angle with the node location upper surface which is greater at a bottom of the contact opening than at a top of the contact opening. In another preferred implementation, the contact opening includes sidewall portions which define a profile which having a non-uniform degree of taper between the contact opening top and bottom. In another preferred implementation, the tapering of the contact opening is effectuated by modifying at least one etching parameter at an intermediate etching point and continuing the etching to outwardly expose the node location.

REFERENCES:
patent: 4488166 (1984-12-01), Lehrer
patent: 5094900 (1992-03-01), Langley
patent: 5180689 (1993-01-01), Liu et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5451819 (1995-09-01), Koyama
patent: 5468342 (1995-11-01), Nulty et al.
patent: 5665623 (1997-09-01), Liang et al.
A. Shinohara et al., "A New Self-Aligned Contact Technology for LLD MOS Transistors", Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, Japan, 1985, pp. 12-15.

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