Method of integrating Ldd implantation for CMOS device fabricati

Details Method of integrating Ldd implantation for CMOS device fabricati Method of integrating Ldd implantation for CMOS device fabricati

1997-10-06

2000-03-28

Meier, S. D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

06043533&

ABSTRACT:
A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step. A semiconductor substrate and an integrated circuit are also disclosed.

REFERENCES:
patent: 5489540 (1996-02-01), Liu

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