Read only/random access memory architecture and methods for oper

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

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Details

365104, 365210, 365156, G11C 1604

Patent

active

058809996

ABSTRACT:
A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided. A sense amplifier having a first input coupled to the first output of the column select pass gates and a second input coupled to the second output of the column select pass gates may be included in the memory device. The memory device may be read by modulating a first voltage input to the sense amplifier using a second voltage input to the sense amplifier.

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