Semiconductor wafer, wafer alignment patterns

Details Semiconductor wafer, wafer alignment patterns Semiconductor wafer, wafer alignment patterns

1997-04-01

1999-07-20

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

438401, 438462, 438975, H01L 23544

Patent

active

059259370

ABSTRACT:
A semiconductor processing method of forming integrated cicuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.

REFERENCES:
patent: 4936930 (1990-06-01), Gruber et al.
patent: 5128283 (1992-07-01), Tanaka et al.
patent: 5300816 (1994-04-01), Lee et al.
patent: 5308682 (1994-05-01), Morikawa
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5614767 (1997-03-01), Ohara
patent: 5618753 (1997-04-01), Tokushima
patent: 5646452 (1997-07-01), Narimatsu

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