Single mask substrate doping process for CMOS integrated circuit

Details Single mask substrate doping process for CMOS integrated circuit Single mask substrate doping process for CMOS integrated circuit

1996-09-19

1999-11-16

Mulpuri, Savitri

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

H01L 21265

Patent

active

059857439

ABSTRACT:
A method of doping a semiconductor substrate with a single masking step. A semiconductor substrate having a first region and a laterally displaced second region is provided. A patterned masking layer is then formed on an upper surface of the semiconductor substrate over the first region. A first well impurity distribution is then formed in the semiconductor substrate such that a peak concentration of the first well impurity distribution is located at a first well depth below the upper surface in the first region of the semiconductor substrate. The peak concentration of the first well impurity distribution within the second region of the semiconductor substrate is located at a depth approximately equal to the first well depth plus a well displacement. A second well impurity distribution is then formed in the semiconductor substrate. A peak concentration of the second well impurity distribution within the second region of the semiconductor substrate is located at a second well depth below the upper surface. A first adjust impurity distribution is then formed in the semiconductor substrate. A peak concentration of the first adjust impurity distribution within the first region of the semiconductor substrate is located at a first adjust depth below the upper surface of the semiconductor substrate. In the second region of the semiconductor substrate, a peak concentration of the first adjust impurity distribution is located at a depth below the upper surface approximately equal to the first adjust depth plus an adjust displacement. A second adjust impurity distribution is then formed in the semiconductor substrate. A peak concentration of the second adjust impurity distribution within the second region of the semiconductor substrate is located at a second adjust depth below the upper surface.

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