Floating gate nonvolatile memory with uniformly erased threshold

Details Floating gate nonvolatile memory with uniformly erased threshold Floating gate nonvolatile memory with uniformly erased threshold

1993-04-01

1995-06-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Erase

365185, 365900, G11C 700, G11C 1602

Patent

active

054249910

ABSTRACT:
A method is described for eliminating overerasure in a nonvolatile memory that includes a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source. The nonvolatile memory is electrically erased until each of the plurality of memory cells has a threshold voltage below a predetermined erased voltage state. The nonvolatile memory then undergoes an equalization programming operation by applying an equalization programming voltage to the control gate of each of the plurality of memory cells such that the threshold voltage of each of the plurality of memory cells is saturated to the predetermined erased voltage state. The equalization programming voltage determines the predetermined erased voltage state. An apparatus for eliminating overerasure in the nonvolatile memory during erasing is also described.

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