Method and apparatus for testing a megacell in an ASIC using JTA

Details Method and apparatus for testing a megacell in an ASIC using JTA Method and apparatus for testing a megacell in an ASIC using JTA

1997-06-27

1998-09-08

Beausoliel, Jr., Robert W.

Excavating

39518306, G01R 3128

Patent

active

058056092

ABSTRACT:
Specially modified JTAG test circuitry is used to provide test inputs and outputs for vendor supplied megacells with buried I/Os within an integrated circuit chip. A multiplexer or similar circuit is used to alternatively select between a JTAG boundary scan output or a megacell circuit test output in response to JTAG instructions within an instruction register. Additionally, a multiplexer or similar circuit is used to alternatively select between an input pin or normal circuitry for input to a megacell's buried input. Furthermore, an AND or OR gate is used to allow test inputs to a megacell, which are normally tied either high or low, to be controlled by an input pin when in the special JTAG test mode. In this manner, test vectors applied at test inputs to the megacell circuitry result in test outputs to the megacell circuitry being provided on output pins of the integrated circuit without requiring additional input and/or output pins that are solely operational as test inputs or outputs to the megacell circuitry.

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IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1193), IEEE Computer Society, "IEEE Standard Test Access Port and Boundary-Scan Architecture",Published by the Institute of Electrical and Electronics Engineers, Inc. Oct. 21, 1993.

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