Semiconductor memory device having improved isolation between el

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

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438240, 438253, 438974, H01L 2120

Patent

active

057364494

ABSTRACT:
With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.

REFERENCES:
patent: 5504041 (1996-04-01), Summerfelt
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5508221 (1996-04-01), Kamiyama
patent: 5605858 (1997-02-01), Nishioka et al.

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