Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Patent
1996-07-10
1998-09-08
Niebling, John
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
438321, 438606, 438926, 438944, 438945, 438951, H01L 21331
Patent
active
058044876
ABSTRACT:
A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa. The sacrificial layer is stripped using an isotropic etch leaving a base ohmic metal region surrounding an emitter mesa at a spacing that is determined by the initial undercut of the sacrificial layer. In an alternate embodiment of the invention, a method is disclosed for controlling the spacing between the base ohmic metal and an emitter ohmic metal.
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Niebling John
Pham Long
TRW Inc.
Yatsko Michael S.
LandOfFree
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