Dielectrically isolated semiconductor devices

Chemistry: electrical and wave energy – Processes and products – Vacuum arc discharge coating

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156 7, 156 17, 29578, 29580, 357 49, 357 50, C23C 1500, H01L 21302, H01L 21314

Patent

active

039665771

ABSTRACT:
The invention is a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer. A layer of silicon dioxide is grown on the back side of the first layer of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the n-type silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.

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L. Maissel et al., Editors, "Handbook of Thin Film Technology" McGraw-Hill, N.Y. 1970, pp. 7-48 to 7-53.

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