Nonvolatile semiconductor memory circuit with high speed read-ou

Details Nonvolatile semiconductor memory circuit with high speed read-ou Nonvolatile semiconductor memory circuit with high speed read-ou

1991-06-26

1994-09-27

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 365185, H01L 2968

Patent

active

053509382

ABSTRACT:
A memory cell transistor includes a semiconductor substrate, a N-type source region, a N-type drain region, a control gate and a P.sup.+ -type emitter region, which is formed in the surface region of the drain region. An insulating film overlies the source region, the drain region, the emitter region, and the control gate. A contact hole is formed in the insulating film so that the surface of the emitter region is exposed. An emitter electrode is formed in and around the contact hole. A PNP vertical bipolar transistor is constituted by the semiconductor substrate serving as a collector region, a P.sup.+ -type buried layer serving as a collector contact, and the drain region serving as a base region.

REFERENCES:
patent: 3893085 (1975-07-01), Hansen
patent: 4247861 (1981-01-01), Hsu et al.
patent: 4435790 (1984-03-01), Tickle et al.

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