System and method of maintaining and utilizing multiple return s

Electrical computers and digital processing systems: processing – Processing control – Branching

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712202, G06F 942

Patent

active

061516716

ABSTRACT:
An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

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