Semiconductor memory device having a pad arrangement with reduce

Details Semiconductor memory device having a pad arrangement with reduce Semiconductor memory device having a pad arrangement with reduce

1997-05-12

2000-11-21

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257784, 257782, 257666, H01L 2348, H01L 2352, H01L 2940

Patent

active

061507288

ABSTRACT:
On a surface of a semiconductor chip having a longer side and a shorter side, a line of a plurality of first pads and a line of a plurality of second pads are arranged in the shape of a cross. Upon multibit expansion, increase in length of the longer side of semiconductor chip can be suppressed even though the number of pads is increased by additionally providing the second pad. In addition, there is no need to reduce the pitch between pads. Thus, a semiconductor memory device allowing multibit expansion is provided without an increase in size of the chip and the pad or reduction in pitches between pads and between pins.

REFERENCES:
patent: H1267 (1993-12-01), Boyd
patent: 4930000 (1990-05-01), Kantz
patent: 5126286 (1992-06-01), Chance
patent: 5250840 (1993-10-01), Oh et al.
patent: 5285082 (1994-02-01), Axer
patent: 5457340 (1995-10-01), Templeton, Jr. et al.
patent: 5545920 (1996-08-01), Russell
patent: 5589420 (1996-12-01), Russell

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