Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-10-30
2000-11-21
Crane, Sara
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257510, 257513, H01L 2701
Patent
active
061506958
ABSTRACT:
A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. The first inter-substrate dielectric includes a local trench. A first local substrate is formed within the local trench. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
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Vol. 2 S. Wolf, Silicon Processing for the VLSI Era, Lattice Press 1990, pp. 341-345.
Gardner Mark
Kadosh Daniel
Wristers Derick J.
Advanced Micro Devices , Inc.
Crane Sara
Kowert Robert C.
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