Method for fabricating MOS transistor having raised source and d

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant

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438300, H01L 2122

Patent

active

061502448

ABSTRACT:
A process for fabricating a semiconductor device comprising a raised source and drain. A semiconductor device is fabricated by a process comprising the following steps: forming active regions separated by isolation regions; forming at each active region a gate electrode structure; depositing a first dielectric layer and a second dielectric layer; removing the top portion of the second dielectric layer to expose the portion of the first dielectric layer that covers the gate electrode structure; forming on the substrate a patterned resist layer to mask portions of the second dielectric layer; forming trenches next to the gate electrode structure by removing the unmasked portions of the second dielectric layer; filling the trenches with a conductor; doping the conductor with dopants; and driving the dopants into the substrate to form the raised source and drain.

REFERENCES:
patent: 4072545 (1978-02-01), De La Moneda
patent: 5773358 (1998-06-01), Wu et al.
patent: 5869375 (1999-02-01), Choi et al.
patent: 5930616 (1999-07-01), Dennison

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