Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-03-16
2000-08-29
Booth, Richard
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438221, 438296, 438300, 438426, 438682, 438683, H01L 218238, H01L 21336, H01L 2176, H01L 2144
Patent
active
061107964
ABSTRACT:
A method of improving junction leakage problem as STI and Salicide processes are performed is provided. The invention is to form a protective insulating layer over STI structure and the periphery of STI structure to prevent penetration of metal ions to eliminate junction leakage problem. First a silicon substrate is provided. A source/drain region and a STI structure are formed in the substrate. A sidewall recess is formed on the upper surface of the STI trench sidewall to expose the substrate. An insulating layer is formed on STI structure, the sidewall recess and the source/drain region. The insulating layer is patterned to cover STI structure and the periphery of STI structure by photolithography and etching processes. The preferred thickness of the insulating layer is thick enough to prevent penetration of metal ions formed during the Salicide process. A Salicide process is performed on the insulating layer and the conductive region.
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patent: 5780348 (1998-07-01), Lin et al.
patent: 5989965 (1999-11-01), Man et al.
Booth Richard
Huang Jiawei
Pompey Ron
United Integrated Circuits Corp.
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