Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-08-07
1996-10-15
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 46, 327160, 327162, H03K 19096
Patent
active
055657974
ABSTRACT:
A device for generating a clock signal includes: a timer unit for generating a period signal that indicates a period defined on the basis of a reference clock and a period control signal; an output unit for reversing an output level thereof in response to the period signal generated by the timer unit and providing a resultant output as a clock signal; and a control unit for producing the period control signal according to the clock signal output from the output unit and controlling the timing of generation of the period signal for the timer unit. A cycle of the clock signal output from the output unit is controlled using the period control signal, so that the cycle corresponds to an odd number of pulse spacings of the reference clock. Owing to this configuration, a deviation of an actual output frequency from a desired output frequency relative to an identical input clock can be minimized, and thus a high-precision output clock can be provided.
REFERENCES:
patent: 4821296 (1989-04-01), Cordell
patent: 5347559 (1994-09-01), Hawkins et al.
patent: 5379325 (1995-01-01), Katayama et al.
patent: 5452323 (1995-09-01), Rosen
First Office Action of Application No. 84108241 Filed Aug. 8, 1995 in R.O.C. and and English Translation thereof.
Fujitsu Limited
Hudspeth David R.
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