Voltage range tolerant CMOS output buffer with reduced input cap

Details Voltage range tolerant CMOS output buffer with reduced input cap Voltage range tolerant CMOS output buffer with reduced input cap

1995-06-23

1996-10-15

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 58, 326 86, 326120, H03K 190185, H03K 190948

Patent

active

055657940

ABSTRACT:
A tri-state CMOS output buffer is provided which exhibits a relatively low input capacitance and tolerance to a range of operating voltages. The output buffer includes a PUP input, a PD input and an output. The output buffer includes a source follower circuit coupled to the PUP input such that the output of the source follower generally follows transitions in the PUP input signal. The source follower output is the buffer output. A pull-down transistor is coupled between the buffer output and ground to pull-down the output voltage when the PD signal goes high. A pull-up transistor and an isolation transistor are coupled in series to form a series coupled circuit. This series-coupled circuit is coupled in parallel with the source follower. The pull-up transistor pulls up the voltage on the buffer output when the PUP input signal goes high. The isolation transistor is switchable to an off state to isolate a parasitic diode associated with the pull-up transistor. A control circuit is coupled to the buffer output and the PUP input to monitor the buffer output and the PUP input to turn off the isolation transistor when the buffer output is in a tri-state condition and the buffer output is driven high by an external device. Otherwise, the control circuit causes the isolation transistor to remain on. In this manner, isolation transistor switching is significantly reduced and the capacitive load presented to the PUP input signal is substantially lowered.

REFERENCES:
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5387826 (1995-02-01), Shay et al.

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