Superscalar microprocessor including a high speed instruction al

Details Superscalar microprocessor including a high speed instruction al Superscalar microprocessor including a high speed instruction al

1997-11-06

1999-11-23

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction alignment

712205, G06F 930

Patent

active

059918691

ABSTRACT:
A superscalar microprocessor having an instruction alignment unit, an instruction cache, a plurality of decode units and a predecode unit is provided. The instruction alignment unit transfers a fixed number of instructions from the instruction cache to each of the plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by the predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions. The instruction alignment unit then shifts and merges the independently produced issue positions to produce a final set of issue positions for transfer to the plurality of decode units.

REFERENCES:
patent: Re35311 (1996-08-01), Vassiliadis et al.
patent: 4044338 (1977-08-01), Wolf
patent: 4396982 (1983-08-01), Wada et al.
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4502111 (1985-02-01), Riffe et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5185868 (1993-02-01), Tran
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5233696 (1993-08-01), Suzuki
patent: 5438668 (1995-08-01), Coon et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5463748 (1995-10-01), Schwendinger
patent: 5465377 (1995-11-01), Blaner et al.
patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5504923 (1996-04-01), Ando
patent: 5513330 (1996-04-01), Stiles
patent: 5526510 (1996-06-01), Akkary et al.
patent: 5559974 (1996-09-01), Boggs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5826053 (1998-10-01), Witt
Intel, "Chapter 2: Microprocessor Architecture Overview," pages 1-2 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," Byte, Jan. 1996, 4 pages.
International Search Report for PCT/US 96/11759 dated Mar. 7, 1997.

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