Semiconductor device having a CMOS element as a buffer

Details Semiconductor device having a CMOS element as a buffer Semiconductor device having a CMOS element as a buffer

1995-12-21

1997-11-11

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 327534, 327565, 327566, H01L 2976, H01L 2994

Patent

active

056867522

ABSTRACT:
A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.

REFERENCES:
patent: 5039877 (1991-08-01), Chern
patent: 5473183 (1995-12-01), Yonemoto
patent: 5510630 (1996-04-01), Agarwal et al.

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