Method and apparatus for maintaining cache coherency in a comput

Details Method and apparatus for maintaining cache coherency in a comput Method and apparatus for maintaining cache coherency in a comput

1997-04-04

1999-03-30

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711146, 711163, 711158, 711145, G06F 1208, G06F 1318

Patent

active

058902007

ABSTRACT:
An apparatus for maintaining cache coherency for snoop operations includes a snoop scheduler coupled to receive addresses from a system bus. The snoop scheduler utilizes a content addressable memory array. The snoop scheduler determines if snoop operations are orthogonal and schedules one or more out-of-order and at least partially overlapping snoop operations. Determining which snoop operations are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.

REFERENCES:
patent: 5168547 (1992-12-01), Miller et al.
patent: 5208914 (1993-05-01), Wilson et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5363498 (1994-11-01), Sakuraba et al.
patent: 5414824 (1995-05-01), Grochowski
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5463753 (1995-10-01), Fry et al.
patent: 5535363 (1996-07-01), Prince
patent: 5566319 (1996-10-01), Lenz
patent: 5572703 (1996-11-01), MacWilliams et al.
patent: 5586331 (1996-12-01), Levenstein
patent: 5611058 (1997-03-01), Moore et al.
patent: 5611071 (1997-03-01), Martinez, Jr.
patent: 5623627 (1997-04-01), Witt
patent: 5623628 (1997-04-01), Brayton
patent: 5623632 (1997-04-01), Liu et al.
patent: 5623670 (1997-04-01), Bohannon et al.
patent: 5657472 (1997-08-01), Van Loo et al.
patent: 5696910 (1997-12-01), Pawlowski
Gharachorloo, et al., "Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors", SIGARCH Computer Architecture News., Apr. 1991, vol. 19, No. 2, p. 246.

Affiliated with

Also associated with

Rating

Method and apparatus for maintaining cache coherency in a comput does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for maintaining cache coherency in a comput, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for maintaining cache coherency in a comput will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1225966