Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-16
1999-03-30
Peeso, Thomas R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395708, 711123, 711125, 711140, 711144, G06F 930
Patent
active
058899960
ABSTRACT:
An apparatus and method for accelerating interpreters, interpretive environments, and the like optimizes the use of caches closest to a processor. An instruction set implementing a virtual machine (interpreter, interpretive environment) is written to fit each instruction at an individual cache line's address in the processor cache. The processor cache may be loaded with the instruction set in a compiled, linked, loaded image. After loading the processor cache, the cache is pinned, locked, disabled from flushing the contents or replacing the contents of any cache line. Faster loading of the processor cache may be achieved by flushing the processor cache and running an application containing all of the instructions of the virtual machine instruction set. Level-1 processor caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention. Examples include Intel's Pentium.TM. class products and Motorola's Power PC Processors.
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Novell Inc.
Peeso Thomas R.
Smith Demetra R.
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