Chip clock skew control method and apparatus

Details Chip clock skew control method and apparatus Chip clock skew control method and apparatus

1993-07-02

1995-11-14

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

257208, H03K 19096

Patent

active

054670330

ABSTRACT:
A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or that communicate such signals to a destination external to the integrated circuit.

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