Instruction fetch unit including instruction buffer and secondar

Details Instruction fetch unit including instruction buffer and secondar Instruction fetch unit including instruction buffer and secondar

1997-01-28

1999-03-30

Harrell, Robert B.

G06F 906

Patent

active

058899863

ABSTRACT:
An instruction fetch unit includes a program buffer for sequential instructions being decoded and a target buffer for an instruction sequence including the target of the next branch instruction. Scan logic coupled to the program buffer scans the program buffer for branch instructions. A target for the first branch instruction is determined and a request to external memory fills the target buffer with a sequence of instructions including a target instruction before sequential decoding reaches the branch instruction. If the branch is subsequently taken, the instructions from the branch target buffer are transferred to the program buffer. The program buffer may be divided into a main and a secondary buffer that have the same size as the target buffer, and an instruction bus between the instruction fetch unit and external memory is sufficiently wide to fill the main, secondary, or target buffer in a single write operation.

REFERENCES:
patent: 4992932 (1991-02-01), Ohshima

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